Telairity-1—Breakthrough Architecture for High Definition Video

The broadcast industry is moving rapidly to all-digital video technology. Among other benefits, digital video allows broadcasters to conserve bandwidth resources by applying digital data compression technology to video streams. Since HD formats involve up to 6 times as many bits as SD formats, the effectiveness of video compression becomes an increasingly important issue as more TV programming shifts from SD to HD.

The requirement for better compression technology driven by new HD formats, in turn, is forcing a shift away from the broadcast industry’s original MPEG-2 standard for digital video compression to more advanced MPEG-4 (Part 10) encoding, commonly know as H.264 or AVC (for Advanced Video Coding). Compared to MPEG-2, the far richer set of encoding tools available in the newer H.264/AVC standard can cut video data rates in half without material loss of image quality.

However, the need for more advanced encoding technology to cope with the swelling stream of video bits caused by the rising use of HD formats places enormous demands on processing resources. While HD formats increase bit streams by a factor of 6, H.264/AVC compression is up to 6 times more compute intensive per bit than MPEG-2 compression. The two effects multiply, meaning up to 36 times more compute capacity is needed to perform H.264/AVC compression on HD formats than MPEG-2 compression on SD formats.

The multi-core Telairity-1 architecture for video processing was designed specifically to address this challenge, supplying the enormous compute resources needed to perform H.264/AVC compression on HD formats in real time, i.e., without the expedient of stretching out the time used by the computational process. The poly-threaded vector/scalar design of the TVP400 processor core is ideally suited to the repetitive, parallelizable algorithms characteristic of video compression and digital imaging applications.

Telairity-1 Block Diagram

Telairity-1 Video Processor

The T1P2000 video processor, the first implementation of the Telairity-1 architecture, is comprised of 5 TVP400 cores, a bit-packing unit, a flexible video I/O controller, and a high-bandwidth DDR2 controller. Each TVP400 core implements 5 separate execution units, namely, a 32-bit scalar pipeline, and 4 16-bit vector engines. The 16-bit length of vector operations reflects the fact that over 90% of all multimedia data is 16-bits or less in length. Exceptional longer data lengths can be handled either by the 32-bit scalar engine, or by chaining together 2 or more of the 16-bit vector engines.

The 4 vector units can each execute up to 5 instructions in parallel: 2 arithmetic-logical operations and 3 memory operations (2 loads, and a store). The 2 arithmetic-logical operations can repeat themselves along their specified vectors anywhere from 1 to 32 times. Added together, the 5 execution engines per core and the 5 cores per processor chip yield a staggering total of over 100 operations per clock cycle, or—at an operating frequency of 594 MHz—a sustainable execution rate of about 50 billion operations per second (50 Gigaops).

Fully Programmable Chip, Software Upgradable Encoders

The T1P2000 video processor is fully programmable. Telairity encoders are implemented in custom dedicated AVClairity software, written in a combination of C and intrinsics, and designed to run directly on the T1P2000, without requiring the services of an intermediate operating system. By eliminating operating system overhead, Telairity encoders are more efficient, faster, and more reliable than encoders implemented to run as applications under an OS on a general-purpose processor.

Since functionality is not hardwired into the T1P2000, changing, adjusting, correcting, or upgrading the operation of Telairity’s encoders is as simple as modifying Telairity’s dedicated AVClairity software. Among other advantages, two benefits stand out. First, regular semiannual releases of AVClairity software enable Telairity encoders to keep pace with the evolving standards for video compression. Second, field upgrades to improve the stability, performance, or functionality of Telairity systems are as simple as downloading a new version of the AVClairity code over the Internet and installing it. The bottom line here is investment protection; since customers are assured that Telairity encoders will remain state-of-the-art throughout their product lifetime.

Highest Level of Integration

The BE8100 incorporates 8 T1P2000 video processors, providing ample horsepower to make Telairity a leader at providing H.264/AVC compression on even the most demanding 1080x1920 video streams in real time. Since 2 processors are ample to do SD encoding (reflecting the 6X smaller frame size of SD formats), the T1P2000 makes the high density BE7400 possible, incorporating 4 SD channels in a 1RU frame size.

The efficiency of Telairity encoders is marked by the fact that they dissipate relatively little heat. As a consequence, they run more reliably (since heat is a leading cause of electronic component failure) and operate quietly, with relatively little fan noise. Further testimonials to their efficiency include the fact that they start encoding within 3 seconds of power-on, and conserve enough board space to allow tor dual redundant power supplies in every model (either standard or as an option).